This invention is generally related to the fabrication of semiconductor devices, and more particularly, to MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) devices having a raised source drain region to gain additional offset control, to lower the parasitic source drain resistance and to improve the thermal management.
It is known in the art that the parasitic source/drain resistance (Rds), i.e., the resistance between the source/drain contact and the inversion layer of a MOSFET is a hindrance to achieving maximum current drive from the MOSFET device. In order to obtain better device performance it is imperative to reduce this resistance Rds. A suggested approach to solving this problem has been to integrate a raised source-drain region (RSD) within the MOSFET device. However, constructing such a structure within a standard CMOS manufacturing process is difficult to achieve.
Several attempts have been made to construct an RSD within a MOSFET device. For instance, in U.S. Pat. No. 5,079,180, an integration process to obtain a raised source/drain transistor is described. First, a spacer is formed and is successively followed by constructing a gate stack, by the formation of a shallow extension and, finally, by the spacer. A selective epitaxy is deposited to raise the region left uncovered by the spacer. Then, a second spacer is positioned adjacent to the first thin sidewall spacer to cover the facet of the raised source-drain region. This step is followed by conventional salicide steps. Several drawbacks are associated with this approach. First, the thermal cycles in the step of constructing the spacers as in the selective epitaxy process often cause the dopant to diffuse in the extension region. The dopant diffusion degrades the transistor short channel effect. Second, with this process flow, the selective epitaxy is formed on a highly doped silicon surface. Accordingly, the highly doped surface changes the epitaxy growth rate which causes the growth rates in n-doped and p-doped to differ. Additionally, in the presence of the dopants the epitaxial surface is rougher than the epitaxial growth. It is therefore imperative that the RSD be formed on top of an undoped surface and to have the extension doping occurring after the RSD formation.
In another U.S. Pat. No. 6,087,235, a similar RSD process is described where the gate is capped during the selective epitxay process. In this manner, the selective epitaxy does not grow on the gate stack, thereby eliminating the problem associated with doping the polysilicon. However, this patent suffers from the same drawbacks associated with the first patent previously described.
In yet another related patent, U.S. Pat. 4,948,745, the fabrication of an elevated source/drain IGFET device is disclosed. A silicon substrate is divided into active and field regions by a field oxide. A gate oxide is formed over the active region and a thin layer of polycrystalline silicon and a thick of silicon nitride are deposited on the gate oxide. The polycrystalline silicon and the silicon nitride are etched to form a stacked structure with the spacers having substantially the same height as the stacked structure, in the pattern of the gate electrode. Sidewall spacers are formed on the edges of the stacked structure and the silicon nitride is removed. Polycrystalline silicon is then deposited onto the polycrystalline silicon and the exposed portions of the source and drain regions to complete the gate electrode and to form the source and drain electrodes. The selectively deposited polycrystalline silicon extends upwardly from the source and drain regions onto the field oxide. The sidewall spacers provide physical and electrical isolation between the gate electrode and the adjacent source and drain electrodes. The structure described herein is affected by the same problems as those discussed previously.
Accordingly, it is an object of the invention to minimize the parasitic source-drain resistance (Rs) of a MOSFET device by constructing a self-aligned raised source drain (RSD) structure using a selective epitaxial process prior to performing any implant step .
It is another object to construct the RSD structure with no additional thermal cycle to minimize diffusing the dopant while improving the short channel effect.
It is a further object to control the offset to minimize the overlap capacitance while optimizing the series resistance (Rs).
This invention proposes an innovative way to form a raised source drain (RSD) prior to any implant steps. The RSD structure thus built has a distinct advantage in that the offset from the RSD to the MOSFET channel is fully adjustable. In this way, the overlap capacitance in the transistor is minimized.
The raised source drain (RSD) construction uses a selective epitaxy process to effectively reduce the Rds. This improvement is even more significant in thin-film SOI technology because an ultra-thin film ( less than 50 nm) introduces a high source drain resistance. Using an RSD, the film outside the channel area thickens which, in turn, reduces the parasitic resistance.
In a first aspect of the invention, there is provided a method of forming a MOSFET device having a raised source-drain region, the method including the steps of: a) forming a notch gate on a top surface of a substrate; b) covering the notch gate and the top surface of the substrate with a conformal dielectric film; c) etching the dielectric film to expose an upper surface of the notch gate and selected exposed areas of the substrate; d) selectively growing silicon on the etched surface of the gate notch and on the etched surface of the substrate; e) implanting doping to form a drain-source area; f) forming spacers on the vertical walls of the notch gate; and g) forming a salicide on the notch gate and on the source and drain areas.
In a second aspect of the invention there is provided a method of forming a MOSFET device having a raised source-drain region, the method including the steps of: a) forming a notch gate on a top surface of a b) covering the notch gate and the top surface of substrate with a conformal dielectric film; c) etching the dielectric film to expose an upper surface of the notch gate and selected exposed areas of the substrate; d) selectively growing silicon on the etched surface of the gate notch and on the etched surface of the substrate; e) implanting doping to form a drain-source area; and f) forming a salicide on the notch gate and on the source and drain areas.